1. Field of the Invention
The present invention relates to an execution processing device, and particularly to an execution processing device which efficiently performs floating-point operations for both variable length representation of an exponent part and fixed length representation of an exponent part.
2. Description of the Prior Art
The floating-point representation is capable of dealing with large numbers and small numbers while maintaining the same precision and is utilized particularly in scientific and technical calculations.
According to the conventional floating-point representation in which the length of the exponent part is fixed, however, the range of numbers to be expressed is limited. Further, even when the value of the exponent part is small and only a small amount of data is required, it was not possible to utilize the space in order to increase the precision of the mantissa part. In order to improve these defects, therefore, it has been desired to develop a floating-point operation relying upon the variable length representation of an exponent part instead of relying upon the fixed length representation of the exponent part.
The floating-point representation usually assumes the form as shown in FIG. 1, wherein reference numeral 1 denotes a sign part that represents the sign of mantissa part, 2 denotes an exponent part, and 3 denotes a mantissa part.
FIG. 2 illustrates a typical example of the conventional floating-point representation.
In FIG. 2, reference numeral 1 denotes a sign part that represents the sign of a mantissa part and that consists of one bit, 4 denotes an exponent part which consists of 7 bits and in which a value is expressed with complement notations of 2, reference numeral 5 denotes a mantissa part of absolute value notation (here, however, the mantissa part is normalized and 1 at the most significant position is concealed) which consists of 24 bits in the case of single precision data or which consists of 56 bits in the case of double precision data, and 6 denotes a separating point between the exponent part and the mantissa part. According to the conventional floating-point representation, the separating point has been fixed between the exponent part and the mantissa part. In performing the arithmetic operation such as addition, subtraction, multiplication and division relying upon the conventional fixed length floating-point representation of the exponent part, therefore, the exponent part and the mantissa part could be easily separated, and the arithmetic operation could be controlled relatively easily since the bit numbers of the exponent part and the mantissa part were fixed.
FIG. 3 illustrates a variable length representation of the exponent part as employed in the present invention, wherein reference numeral 1 denotes a sign part, 6 denotes a separating point, 7 denotes a first exponent part (often called the front part of the exponent part), 8 denotes an exponent part length dividing part, 9 denotes a second exponent part (often called the back part of the exponent part), and 10 denotes a mantissa part.
According to the variable length representation of the exponent part as shown in FIG. 3, though the total number of bits of the sign part, the exponent part and the mantissa part is fixed, the bit length of the exponent part and the mantissa part varies within the limited range, i.e., the separating point moves between the exponent part and the mantissa part, as will be mentioned later in detail.
Therefore, although the above-mentioned advantage is obtained, the arithmetic operation is controlled in a more complex manner than in the case of the fixed length representation of the exponent part.
Further, almost all of the scientific and technical programs developed thus far are based upon the fixed length data of the exponent part. Accordingly, the execution processing device must be constructed so as to be capable of executing the operations of fixed length data of the exponent part in addition to the operations of variable length data of the exponent part. In this case, however, it becomes more complex to control the arithmetic operation. Moreover, operations of the two data must be executed, and instructions are required in two sets to distinguish the instruction which designates loading of the two data from the memory and the instruction which designates storing the results of two arithmetic operations.
Hereinafter, the fixed length representation of the exponent part and the fixed length data of the exponent part are simply referred to as fixed length representation and fixed length data, and variable length representation of the exponent part and variable length data of the exponent part are simply referred to as variable length representation and variable length data.